Alif Semiconductor /AE302F80F5582AE_CM55_HP_View /I2C0 /I2C_DMA_RDLR

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Interpret as I2C_DMA_RDLR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DMARDL

Description

DMA Transmit Data Level Register

Fields

DMARDL

Receive Data Level. This field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL + 1; that is, I2C_DMA_RX is generated when the numberof valid data entries in the Rx FIFO is equal to or more than this field value + 1, and I2C_DMA_CR[RDMAE] is set to 0x1. For instance, when IC_DMA_RDLR[DMARDL] is set to 0x0, then I2C_DMA_RX is asserted when 1 or more data entries are present in the Rx FIFO.

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